Hi Kevin,

Suppose I wanted to model JUST the capacitance portion of a diode? No
DC current, etc.

The equation "fold-over" at VD~FC*VJ looks to be PITA to implement.

Maybe you know of a way to trick a full diode model into not doing its
DC thing ?:-}

...Jim Thompson
--
| James E.Thompson | mens |
| Analog Innovations | et |
| Analog/Mixed-Signal ASIC's and Discrete Systems | manus |
| San Tan Valley, AZ 85142 Skype: skypeanalog | |
| Voice480)460-2350 Fax: Available upon request | Brass Rat |
| E-mail Icon at http://www.analog-innovations.com | 1962 |

I love to cook with wine. Sometimes I even put it in the food.

In article , To-Email-Use-
says...

Hi Kevin,

Suppose I wanted to model JUST the capacitance portion of a diode? No
DC current, etc.

The equation "fold-over" at VD~FC*VJ looks to be PITA to implement.

Maybe you know of a way to trick a full diode model into not doing its
DC thing ?:-}

...Jim Thompson

Come on jim, you are suppose to be the Simulation king!

..model NewName ExistingModelName (N=1000000)

Weeee.. At least that removes the forward out of it

Jamie

I've seen big EG or VJ or something combined with IS=1e-36 or something
like that. MOSFET Cdg models.

Tim

--
Seven Transistor Labs
Electrical Engineering Consultation
Website: http://seventransistorlabs.com

"Jim Thompson" wrote
in message ...
Hi Kevin,

Suppose I wanted to model JUST the capacitance portion of a diode? No
DC current, etc.

The equation "fold-over" at VD~FC*VJ looks to be PITA to implement.

Maybe you know of a way to trick a full diode model into not doing its
DC thing ?:-}

...Jim Thompson
--
| James E.Thompson | mens |
| Analog Innovations | et |
| Analog/Mixed-Signal ASIC's and Discrete Systems | manus |
| San Tan Valley, AZ 85142 Skype: skypeanalog | |
| Voice480)460-2350 Fax: Available upon request | Brass Rat |
| E-mail Icon at http://www.analog-innovations.com | 1962 |

I love to cook with wine. Sometimes I even put it in the food.

"Jim Thompson" wrote in message
.. .
Hi Kevin,

Suppose I wanted to model JUST the capacitance portion of a diode? No
DC current, etc.

The equation "fold-over" at VD~FC*VJ looks to be PITA to implement.

Maybe you know of a way to trick a full diode model into not doing its DC
thing ?:-}

I agree with the post by Maynard, making N large will turn it off.

I=IS(1- exp(qV/KTN) )

N=100 keeps it off for up to 10V

Can be handy to keep some IS for convergence.

Kevin Aylward
www.kevinaylward.co.uk
www.anasoft.co.uk - SuperSpice

On Fri, 17 Oct 2014 02:06:47 -0500, "Tim Williams"
wrote:

I've seen big EG or VJ or something combined with IS=1e-36 or something
like that. MOSFET Cdg models.

Tim

This is in regard to my pursuit of an accurate model for forward and
reverse recovery... large voltages preclude setting IS very small, it
still conducts some unwanted current.

I'll solve it... TANH to the rescue :-}

...Jim Thompson
--
| James E.Thompson | mens |
| Analog Innovations | et |
| Analog/Mixed-Signal ASIC's and Discrete Systems | manus |
| San Tan Valley, AZ 85142 Skype: skypeanalog | |
| Voice480)460-2350 Fax: Available upon request | Brass Rat |
| E-mail Icon at http://www.analog-innovations.com | 1962 |

I love to cook with wine. Sometimes I even put it in the food.

On Fri, 17 Oct 2014 16:04:10 +0100, "Kevin Aylward"
wrote:

"Jim Thompson" wrote in message
. ..
Hi Kevin,

Suppose I wanted to model JUST the capacitance portion of a diode? No
DC current, etc.

The equation "fold-over" at VD~FC*VJ looks to be PITA to implement.

Maybe you know of a way to trick a full diode model into not doing its DC
thing ?:-}

I agree with the post by Maynard, making N large will turn it off.

I=IS(1- exp(qV/KTN) )

N=100 keeps it off for up to 10V

Can be handy to keep some IS for convergence.

Kevin Aylward
www.kevinaylward.co.uk
www.anasoft.co.uk - SuperSpice

Aha! I didn't think about "N"

...Jim Thompson
--
| James E.Thompson | mens |
| Analog Innovations | et |
| Analog/Mixed-Signal ASIC's and Discrete Systems | manus |
| San Tan Valley, AZ 85142 Skype: skypeanalog | |
| Voice480)460-2350 Fax: Available upon request | Brass Rat |
| E-mail Icon at http://www.analog-innovations.com | 1962 |

I love to cook with wine. Sometimes I even put it in the food.

On Thu, 16 Oct 2014 16:10:47 -0700, Jim Thompson
wrote:

Hi Kevin,

Suppose I wanted to model JUST the capacitance portion of a diode? No
DC current, etc.

The equation "fold-over" at VD~FC*VJ looks to be PITA to implement.

Maybe you know of a way to trick a full diode model into not doing its
DC thing ?:-}

...Jim Thompson

Isn't that just a nonlinear capacitor?


Version 4
SHEET 1 1096 680
WIRE 48 80 0 80
WIRE 176 80 48 80
WIRE 320 80 240 80
WIRE 480 80 320 80
WIRE 576 80 528 80
WIRE 624 80 576 80
WIRE 0 144 0 80
WIRE 320 144 320 80
WIRE 528 144 528 80
WIRE 480 160 480 80
WIRE 0 272 0 224
WIRE 320 272 320 224
WIRE 480 272 480 208
WIRE 528 272 528 224
FLAG 0 272 0
FLAG 320 272 0
FLAG 480 272 0
FLAG 528 272 0
FLAG 576 80 CAP
FLAG 48 80 RAMP
SYMBOL res 304 128 R0
WINDOW 0 49 47 Left 2
WINDOW 3 50 78 Left 2
SYMATTR InstName R1
SYMATTR Value 1µ
SYMBOL voltage 0 128 R0
WINDOW 0 68 65 Left 2
WINDOW 3 17 112 Left 2
WINDOW 123 0 0 Left 2
WINDOW 39 0 0 Left 2
SYMATTR InstName V1
SYMATTR Value PULSE(0 100 0 100)
SYMBOL e 528 128 R0
WINDOW 0 64 53 Left 2
WINDOW 3 58 85 Left 2
SYMATTR InstName E1
SYMATTR Value 1e6
SYMBOL cap 176 96 R270
WINDOW 0 -43 32 VTop 2
WINDOW 3 77 35 VBottom 2
SYMATTR InstName C1
SYMATTR Value q = x / (1+2*x)
TEXT 16 112 Left 2 ;1 V/S
TEXT 560 112 Left 2 ;1 V / F
TEXT 368 8 Left 2 !.tran 0 1 0
TEXT 8 -96 Left 2 ;Nonlinear Capacitor C:V Curve
TEXT 48 -56 Left 2 ;J Larkin August 11, 2014
TEXT 480 -96 Left 2 ;Cap is 1F at low voltage
TEXT 536 -56 Left 2 ;0.1F at 1 volt











--

John Larkin Highland Technology, Inc

jlarkin att highlandtechnology dott com
http://www.highlandtechnology.com

On Fri, 17 Oct 2014 09:08:45 -0700, John Larkin
wrote:

On Thu, 16 Oct 2014 16:10:47 -0700, Jim Thompson
wrote:

Hi Kevin,

Suppose I wanted to model JUST the capacitance portion of a diode? No
DC current, etc.

The equation "fold-over" at VD~FC*VJ looks to be PITA to implement.

Maybe you know of a way to trick a full diode model into not doing its
DC thing ?:-}

...Jim Thompson

Isn't that just a nonlinear capacitor?


Version 4
SHEET 1 1096 680
[snip]
TEXT 8 -96 Left 2 ;Nonlinear Capacitor C:V Curve
TEXT 48 -56 Left 2 ;J Larkin August 11, 2014
TEXT 480 -96 Left 2 ;Cap is 1F at low voltage
TEXT 536 -56 Left 2 ;0.1F at 1 volt

The diode _junction_ capacitance has two separate equations with a
break-point set by FC.

I _could_ implement it using one of my TANH blenders, but the
Maynard/Aylward method, set N=100 makes it trivial... let Spice manage
the zone problem.

Would you be interested in conducting some diode recovery time
experiments? As I'm developing this model, I'm trying to match up the
coefficients with measured and datasheet terms... so that they drop
right into the subcircuit.

...Jim Thompson
--
| James E.Thompson | mens |
| Analog Innovations | et |
| Analog/Mixed-Signal ASIC's and Discrete Systems | manus |
| San Tan Valley, AZ 85142 Skype: skypeanalog | |
| Voice480)460-2350 Fax: Available upon request | Brass Rat |
| E-mail Icon at http://www.analog-innovations.com | 1962 |

I love to cook with wine. Sometimes I even put it in the food.

"Jim Thompson" wrote in message
...

On Fri, 17 Oct 2014 16:04:10 +0100, "Kevin Aylward"
wrote:

"Jim Thompson" wrote in message
. ..
Hi Kevin,

Suppose I wanted to model JUST the capacitance portion of a diode? No
DC current, etc.

The equation "fold-over" at VD~FC*VJ looks to be PITA to implement.

Maybe you know of a way to trick a full diode model into not doing its DC
thing ?:-}

I agree with the post by Maynard, making N large will turn it off.

I=IS(1- exp(qV/KTN) )

N=100 keeps it off for up to 10V

Can be handy to keep some IS for convergence.



Aha! I didn't think about "N"

Its the parameter that needs setting to get the correct higher voltage of
LEDs. Often IS is used, incorrectly.

Kevin Aylward
www.kevinaylward.co.uk
www.anasoft.co.uk - SuperSpice